Background

In high school, I took a course covering the basics of Computer Architecture, which you can read more about here. In this project, I designed a rudimentary 16-bit CPU using HACK HDL (which is similar to VHDL). This CPU had no hazard handling, was single cycle, and used a bespoke ISA. While the software components of the project were definitely interesting, the hardware components were by far the most interesting and eye-opening. To encounter the same issues that the historical names in computer engineering encountered decades prior and learning about their solutions was awe-inspiring.

When I entered college, I expected to be able to learn more about these topics of digital design, computer architecture, and operating system software. However, to my disappointment, OSU’s (my current school) computer engineering curriculum is largely non-existent, and is more or less an amalgamation of electrical engineering and computer science majors, with very few courses focused on computer engineering. To add insult to injury, the few courses that cover topics of interest, are typically understaffed, underfunded, with outdated curricula and therefore poorly taught. While this is frustrating, I have always been of the belief that I can learn anything myself, and cannot rely on institutions to educate me; so I decided to teach myself.

Abstract

The initial goals of this first phase of this project (which I plan to complete before Jan 8th 2026) are the following:

1. Learn SystemVerilog.
2. Learn fundamentals of computer architecture, digital design, and VLSI.
3. Implement a single cycle CPU
4. Implement a 5-stage pipelined CPU with hazard handling.

While these are the initial goals, the end goal of the project is to design a superscalar parameterizable CPU with exception and hazard handling which incorporates modern features like Out-of-Order execution, branch prediction, caching, and maybe even multiple cores. This end goal currently seems insurmountable, but I am confident that if I put in the time, it will be possible.

Current Progress

I have already completed 3/4 of the tasks for this phase. Usually when I look for resources to teach myself, I turn to YouTube and dedicated websites with interactive activities, but since this topic is not something people do as a hobby and is relatively niche, it was extremely difficult to find resources, let along high-quality and updated ones. Luckily, I was able to find textbooks that were fairly up-to-date and very high quality. Textbooks generally lack more advanced topics beyond pipelining, but for this first phase, relying solely on textbooks is very much possible.

So far, I have taught myself SystemVerilog using a combination of a couple textbooks and a resource from the University of Toronto called HDLbits. I experimented further by using Icarus Verilog to simulate circuits and debugged them using Surfer (a very nice waveform viewer). I was able to steal find some course materials from other universities like CMU to supplement my learning. It was fairly easy with the resources and prior knowledge I had to implement a single-cycle 32-bit ARM CPU, which I validated myself with custom test benches.

I chose ARM because I thought “Oh ARM is the big hot architecture right now” along with the main textbook I was using focusing on ARM. Also, MIPS was the primary alternative, which is not used nearly as much in industry as far as I know, and is also proprietary. However, I have now learned that further down the line, it will be harder to sustain solo-development on the ARM ISA since many tools for design and validation are locked behind closed doors due to its proprietary nature, which is why I am switching to RISC-V for my pipelined CPU and likely for all future CPUs I design in this project.

Dev log

As I said in the note at the top of the page, I am implementing a Dev-Log feature into my site to add support for easily navigable sub-posts for long-term projects like this. I have most of the content for the first 3 tasks that I have completed, detailing the considerations I made, the challenges I encountered and my results. My priority lies in completing this project rather than writing about it, but it will be done soon™.