The NSA (No Such Agency) provided a contract to OSU’s Computer Science and Engineering department to develop a communications system. This project was sponsored by the DIU (Defense Innovation Unit). This was an unconventional research role as the PI was not a professor and the research burden primarily fell onto me. This however meant i was given a lot of freedom to pursue the directions I found interesting.
The project was spearheaded by the NSA’s cryptography team which provided the mathematical specifications of cascading Feistel ciphers along with requirements for jam-resistance. The objective of the project was to implement a multi-user FHSS (Frequency Hopping Spread Spectrum) UHF (Ultra High Frequency) that used cryptographic seeds for planning frequency hops along with sending all information in encrypted chunks.
Architecture
In the modern day, opponents not longer attempt to crack each other’s communication due to the strength of modern encryption and the frequency of key changes. Instead, opponents will often monitor channels for activity that is not their own, and jam them to prevent their opponent from communicating entirely. The goal of FHSS communication is to change the communication channel rapidly across pseudorandom frequencies so the enemy cannot discern communication from background noise. Furthermore, even if the enemy does detect it, the hops should be fast enough that by the time the enemy identifies the current active channel and tunes a jammer to said channel, the communication system has already hopped to a new channel.
Since this is a multi-user system, the ciphers included logic to prevent friendly users from colliding on the same channel. I will add more details about the ciphers once I know exactly what I can and cannot release. I did make modifications to the ciphers during implementation that improved their security and made them easier to implement on hardware.
To maximize the hopping rate, I chose to architect the entire communications system on SDR FPGAs. This made it so the only limitation was the tuning and dwell time of the RFIC. I was able to further minimize the dwell time by using fast lock profiles, which the AD9361, though it only 8 slots by default. I got around this limitation by converting a significant portion of the FPGA’s BRAM to serve as registers for thousands of additional profiles slots in a sorted LUT allowing for quick access. This required replacing the default front end which relied on a NIOS II softcore processor.
Keeping throughput high with the intermittent hops and acks meant efficient data transmission was paramount. The usable symbol rate of the system was quite low compared to traditional continuous single channel communication. To counteract this, I implemented QAM-256, allowing for 8 bits of data per symbol.
Conclusion
I will flesh out more details on this page about the full architecture once I get approval to share additional details. I had to make a lot of interesting optimizations in this project and learned quite a bit of how FPGAs and SDRs work.